RISC-V processor
A C++ simulator and SystemVerilog implementation (the latter is still a WIP) of the RISC-V 32IM architecture that I developed to learn about RISC-V.
GitHubHex processor
The Hex Architecture is a very simple processor intended for explaining how a computer works. This repository contains an implementation in Verilog and basic tooling written in C++ for developing programs (a compiler, assembler and simulator). It was written out of curiosity and to serve as an example of how high-level programs relate to the underlying hardware implementation.
GitHub DocumentationPRNG testing
This repository contains facilities for comprehensively testing PRNGs using statistical test suites. It provides a facility to run a PRNG against TestU01, PractRand and Gjrand, with parallel runs from different seeds and permutations of the output bits, and a script for summarising results across all the runs. This testing methodology was used for the investigation in this paper.
GitHubHome energy data
A Python-based project that I use to analyse data exported from my Vaillant heat pump monitoring. It reads in the raw CSV files produced by the Vaillant smartphone app and renders a set of charts and statistics in HTML.
GitHubPersonal finances
A Python-based project that I use to fetch personal finance data (collected transactions from bank accounts and credit cards etc) held in Google Sheets and then generate a set of summary HTML reports including tables and charts.
GitHubNetlist Paths
Netlist Paths is a library and command-line tool for querying a Verilog netlist. It reads an XML representation of a design’s netlist, produced by Verilator, and provides facilities for inspecting types, variables and paths. The library is written in C++ and has a Python interface. This project has now been superseded by Slang Netlist (see above).
GitHub DocumentationSire compiler
An implementation of a language and runtime system for dynamic process creation. There are two versions: an initial one written in C that directly targeted the XMOS XS1 architecture, and a rewrite in Python targeting XS1 via the XC language.
Revised version Original version