Computing

Various talks and papers that I’ve produced since 2014.

A Fast Hardware Pseudorandom Number Generator Based on xoroshiro128,
With Stephen Felix, in IEEE Transactions on Computers, 2022, doi: 10.1109/TC.2022.3204226 (preprint on arXiv).

Netlist Paths: a tool for front-end netlist analysis,
With Samuel Kong, DVCon Europe, October 2021 (presentation slides, extended abstract).

Error-correcting codes,
A presentation introducing ECC schemes and SECDED implementation in hardware, May 2020.

New chips for machine intelligence,
A guest lecture given to the University of Bristol Advanced Computer Architecture class, November 2019.

netlist-paths: A command line tool for querying paths in a Verilog design,
A lightning talk presented at ORConf 2019 in Bordeaux, France (video on YouTube).

Compiling for dual issue on the XMOS XS2 processor,
A presentation given at an ENTRA project meeting, May 2015.

Scalable data abstractions for distributed parallel computations,
A presentation given to the Software Performance Optimisation group, Imperial College London. January 2013.

The resurgence of parallel programming languages,
A presentation given at the BCS Advance Programming Specialist Group, London. April 2012.

Other

Next Generation Innovation Lab. C.H.E.E.S.E.,
A talk given with Mike Andrews for the Next Generation Innovation Lab webinar series, March 2021 (video on YouTube).

An overview of The CHEESE Project,
A talk given for the High Kingsdown Eco program, January 2020.

University

Documents from my undergraduate and PhD degrees.

Emulating a large memory with a collection of smaller ones,
Unpublished paper, 2014 (arXiv).

Scalable abstractions for general-purpose parallel computation,
Ph.D. Thesis, University of Bristol. March 2014.

The Sire programming language definition and syntax
Excerpts from my Ph.D. thesis, 2014.

Scalable data abstractions for distributed parallel computations,
Unpublished paper, 2012 (arXiv).

Fast distributed process creation with the XMOS XS1 architecture,
Communicating Process Architectures, University of Limerick. June 2011 (arXiv, slides).

A network simulator with reconfigurable routing and topology,
User guide, 2011 (GitHub).

The XMOS XK-XMP-64 development board,
Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on, Pittsburgh, PA, 2011, pp. 255-256.

Dynamic generation of parallel computations,
UK Electronics Forum, Newcastle University, June 2010 (slides).

XMP-64 performance experiments,
XMOS technical report, 2010 (GitHub).

Universal routing in processor networks,
Masters Thesis, University of Bristol. May 2009.